At present, such systems for processing video and graphics images are focused on cost optimization. Moreover, they require high video quality, but also the use of graphics planes to display, in particular, menus on the television screens and thus to add interactivity to all the programs.
The cost of such a processing system is in part defined by the choice of external memories. Also, memories of the SDRAM type which are low cost are preferably used. Such memories offer a small bandwidth, which entails optimizing the system with respect to this small bandwidth criteria.
To remedy this bandwidth problem, but also to comply with the pixel processing constraints which, in television applications, should be performed at a frequency of 13.5 MHz and sometimes more to allow rescaling, the present systems are designed to minimize the number of pixel manipulations.
With this in mind, such video and graphics data processing systems comprise units which create the pixels and store the images thus created in the external memory. For example, such units are MPEG, JPEG decoders, microprocessors, or graphics accelerators that allow the creation of graphics objects with the aid of simple functions, such as the filling in of a rectangle, or the copying of an object, or the mixing of two objects.
Aside from these pixel creating units, the system also comprises units, for example, of the DMA type. These units will extract the pixels thus generated from the external memory, for example the SDRAM memory, and send them to a pixel compositor whose role is to compose all the planes (or layers) intended to form the image before sending it to a display device, such as a television screen, for example.
Also, each unit of the DMA type, is dedicated to a particular type of plane of the image, for example, a video plane or a graphics plane, and is optimized to extract this plane with a predetermined format.
Such an architecture is efficient in terms of bandwidth, since the manipulation of the pixels is reduced to the minimum. In fact, over the duration of a frame or an image, the video decodings and the graphics planes are effected, whereas they are accessed during the next image or frame and composed together. It therefore follows that the external memory is used once to store all the planes and once to read them before mixing or composition.
However, the arrival of new memories of the DDR/SDRAM type, for example, now makes such an architecture obsolete and expensive. Specifically, its main drawback then resides in its footprint. More precisely, depending on the number of planes used by the application, each unit of the DMA type may require processes for redimensioning, anti-flicker or color conversion. Also, these processes lead to a parallelization of the resources that is extremely expensive in terms of surface area.
Moreover, the pixel compositor has to be designed to combine all the graphics planes with video planes. Such a compositor is composed of a large number of multipliers, and this also has a negative impact on the surface area.
Moreover, since an item of hardware is dedicated to each plane, once the configuration has been chosen, the integrated circuit (ASIC) is no longer flexible and any change in the specifications thus translates into a change in the hardware.
Furthermore, to avoid pixel manipulations, all the units of the DMA type operate at the television sampling frequency or at a multiple of this sampling frequency (13.5 MHz or 27 MHz). Also, to avoid non-delivery of pixels to the television screen, it is then advisable to take account of a large number of real-time constraints, which leads to the system being complicated further.